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DATA SHEET
SAA4945H LIne MEmory noise Reduction IC (LIMERIC)
Preliminary specification File under Integrated Circuits, IC02 1997 Jun 10
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
FEATURES * 2-D adaptive vertically recursive noise reduction * Noise reduction for Y, U and V signals in 4 : 1 : 1 format * Single 5 V 10% power supply * Communication by means of serial communication protocol 83C654 (SNERT bus) * Via SNERT bus, 10 different types of noise reduction selectable; the noise reduction function can also be disabled * Phase relation write enable input/output signal simultaneously switchable over one clock period w.r.t. input/output samples * 8-bit wide data processing for Y, U and V; in unsigned format (Y signal) and in 2's complement (U and V signals) * One fixed line locked clock operation frequency up to 16 MHz (typical) * Exactly one line delay. QUICK REFERENCE DATA SYMBOL VDD IDD P fCLK fSNERT Tamb Note 1. Maximum number of clocks per line is 1024. ORDERING INFORMATION TYPE NUMBER SAA4945H PACKAGE NAME DESCRIPTION PARAMETER supply voltage (pins 5, 29 and 30) supply current power dissipation clock frequency bus clock frequency operating ambient temperature 7%; note 1 CONDITIONS - - 10 - 0 MIN. 4.5 70 350 16 - - TYP. 5.0 - - GENERAL DESCRIPTION
SAA4945H
The SAA4945H, LIMERIC (LIne MEmory noise Reduction IC) is a 2-D recursive noise reduction filter for both luminance and colour difference signals. The noise reduction is automatically adapted to the global noise level in the image. Ten different preferences of noise reduction can be set using a synchronous receiver transmitter bus; SNERT (Synchronous No parity Eight bit Receive Transmit) bus. Alternatively, the noise reduction can be switched off. The LIMERIC is generally placed directly after the ADC in the feature box and works fully in the 1fh (50/60 Hz) domain.
MAX. 5.5 V
UNIT mA mW MHz MHz C
17.1 1 70
VERSION
QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
BLOCK DIAGRAM
SAA4945H
handbook, full pagewidth
VDD1 5
VDD2 29
VDD3 30
UI0, UI1 VI0, VI1
16, 15 18, 17 REFORMATTER
NOISE REDUCTION FILTER (MULTIPLEXED)
36, 37 RAM_UV t FORMATTER 34, 35
UO0, UO1 VO0, VO1
N_thr_UV NOISE REDUCTION FILTER N_thr_Y 8 N_thr_UV
14 to 7 YI0 to YI7
8
RAM_Y
38 to 44, 1
YO0 to YO6, YO7
SAA4945H
TEST CONTROL
26 25 24
NOISE ESTIMATOR YpScale TASTE NTHR internal control signals
TST0 TST1 TST2
SNERT INTERFACE
Wval
CONTROL
31 33
WEO n.c.
2 SDNA
3
4
19 21 22 CLK Va WEI
6
20
23
27
28
32
VRST SNCL
GND2 GND4 GND6 GND3 GND5 GND1
MGK170
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
PINNING SYMBOL YO7 SNDA SNCL VRST VDD1 GND1 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UI1 UI0 VI1 VI0 CLK GND2 WEI Va GND3 TST2 TST1 TST0 GND4 GND5 VDD2 VDD3 WEO GND6 n.c. VO0 VO1 UO0 UO1 YO0 YO1 YO2 1997 Jun 10 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TYPE output input/output input input supply ground input input input input input input input input input input input input input ground input input ground input input input ground ground supply supply output ground - output output output output output output output luminance output bit 7 data from interface SNERT bus clock from interface SNERT bus reset in the vertical blanking interval supply voltage 1 ground 1 DESCRIPTION
SAA4945H
luminance input bit 7 from analog-to-digital converter luminance input bit 6 from analog-to-digital converter luminance input bit 5 from analog-to-digital converter luminance input bit 4 from analog-to-digital converter luminance input bit 3 from analog-to-digital converter luminance input bit 2 from analog-to-digital converter luminance input bit 1 from analog-to-digital converter luminance input bit 0 from analog-to-digital converter U input bit 1 from analog-to-digital converter U input bit 0 from analog-to-digital converter V input bit 1 from analog-to-digital converter V input bit 0 from analog-to-digital converter master clock ground 2 write enable input vertical blanking pulse ground 3 test pin 2 test pin 1 test pin 0 ground 4 ground 5 supply voltage 2 supply voltage 3 write enable output ground 6 not connected V output bit 0 V output bit 1 U output bit 0 U output bit 1 luminance output bit 0 luminance output bit 1 luminance output bit 2 4
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
SYMBOL YO3 YO4 YO5 YO6 PIN 41 42 43 44 TYPE output output output output luminance output bit 3 luminance output bit 4 luminance output bit 5 luminance output bit 6 DESCRIPTION
SAA4945H
37 UO1
36 UO0
44 YO6
43 YO5
42 YO4
41 YO3
40 YO2
39 YO1
38 YO0
35 VO1
handbook, full pagewidth
34 VO0
YO7 1 SNDA 2 SNCL 3 VRST 4 VDD1 5 GND1 6 YI7 7 YI6 8 YI5 9 YI4 10 YI3 11
33 n.c. 32 GND6 31 WEO 30 VDD3 29 VDD2
SAA4945H
28 GND5 27 GND4 26 TST0 25 TST1 24 TST2 23 GND3
WEI 21
YI2 12
YI1 13
YI0 14
UI1 15
UI0 16
VI1 17
VI0 18
CLK 19
GND2 20
Va 22
MGK169
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
FUNCTIONAL DESCRIPTION The digital LIMERIC is an effective low noise reduction IC for luminance and colour difference signals. Noise filtering is automatically adapted to the global noise level which is measured within the picture content. The two dimensional non-linear noise reduction (one for luminance, one for chrominance) uses only line memory to function. Furthermore, up to 10 different preferences can be set by the user. As shown in Fig.1, the main components of the device are the noise reduction filter with the line memories (RAM) and the noise estimator. Other components shown are the reformatter, formatter, controller and a SNERT bus transceiver. Noise reduction filter Both luminance and chrominance signals are filtered with vertical recursion. This is produced as the filter receives both filtered samples from the previous line, and unfiltered samples from the current line. A new replacement value is calculated for each sample read from the line memory. This in turn, is the filtered response value for the reference input pixel. The reference pixel is then placed at the centre of the delay-line into which the current (unfiltered) video line is shifted. Tables 1 to 6 show this as an `O'. Both luminance and colour difference signals are filtered using the so-called Discriminating Averaging Filter (DAF), in which filter coefficients are related to the Absolute Difference (AD) between samples. The filter uses samples from both present and previous line (using the line delay) and the result of the filter is stored back in the line memory. In this way a vertical recursive structure is realized. The filter coefficients are set depending on the noise measured by the noise estimator or the NTHR (SNERT register F9). CHROMINANCE FILTER The basic signal processing for either U or V is via the same filter. It is used to process both V and U using a multiplexed operation. The taps structure of the chrominance filter is as shown in Table 1. Table 1 Chrominance processing 5 adjacent R - Y samples from the filtered line 3 adjacent R - Y samples from the incoming line 6 LUMINANCE FILTER
SAA4945H
The taps structure of the luminance filter is as shown in Table 2. Table 2 Luminance processing 5 Y samples from the filtered line (distance 4 / 5 pixel) 3 Y samples from the incoming line (distance 2 pixels)
X....X...X...X....X
o.O.o
A `weave' function is used to reduce any smearing effect that could occur at edges. As shown in Tables 3 to 6, the `weave' calculates over 4 consecutive lines. The relative position of the actual pixel changes one position every line. Table 3 For line 2n X....X...X...X....X o.O.o Table 4 For line 2n + 1 X....X...X...X....X ..o.O.o Table 5 For line 2n + 2 X....X...X...X....X o.O.o Table 6 For line 2n + 3 X....X...X...X....X o.O.o.. Table 7 Weave configuration Depending on even and odd fields the `weave' has the following configuration: ODD FIELDS X X X X X X X X X X X X X EVEN FIELDS X
XXXXX oOo
1997 Jun 10
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
Noise estimator
SAA4945H
The threshold value N_thr for the filters is calculated in the noise estimator block (see Fig.3). There are four options for producing the N_thr value: 1. Pre-filter gain setting (YpScale) 2. Wval selects the sensitivity of the noise estimator 3. TASTE (TS) scales the N_thr linear 4. NTHR is externally applied when the noise estimator is disabled by the control bit ExThr of the Status Register.
handbook, full pagewidth
YI
PRE-FILTER
NOISE ESTIMATOR
x
4 NTHR
MUX
N_thr
YpScale
Wval
TS0-TS3
ExThr
MGK171
Fig.3 Noise estimator.
SIGNAL DESCRIPTION Input signals YI7 TO YI0 (PINS 7 TO 14) * Eight bit wide digital luminance input bus * Unsigned data; dynamic range between 0 and 255 * The maximum number of input samples equals 852 active samples/line. UI1 AND UI0 (PINS 15 AND 16) * Colour difference signal U * Data in 2's complement; dynamic range between -128 and +127 * Y : U : V format 4 : 1 : 1; see Table 8 for input data coding * The maximum number of input samples equals 213 samples/line * Internal data processing of U signals in unsigned format.
VI1 AND VI0 (PINS 17 AND 18) * Colour difference signal V * Data in 2's complement; dynamic range between -128 and +127 * Y : U : V format 4 : 1 : 1; see Table 8 for input data coding * The maximum number of input samples equals 213 samples/line * Internal data processing of V signals in unsigned format.
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
Table 8 Input /output data coding INPUT Y Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U V UI1 UI0 VI1 VI0 WEI (PIN 21) * Write enable input * Write enable indicates the time when active input samples (Y, U and V) are present * Timing relation (see Fig.4) depending on the logic level of the Write Enable Select signal (WES) in status register; to adapt to different external video memories BIT Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 INPUT DATA SEQUENCE Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U 03 U 02 V03 V02
SAA4945H
Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00
* The number of input samples is a multiple of 4 (see Fig.4) * Start of new line indicated by write enable signal LOW for at least 4 consecutive clock periods (see Fig.4) * During active line, WEI is not allowed to be LOW for more than 1 clock cycle.
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
SAA4945H
handbook, full pagewidth CLK
WEI (WES = 0 status register) line n WEI (WES = 1 status register) YI0 to YI7 UI0, UI1 VI0, VI1 X Y0 U0. 7,6 V0. 7,6 Y1 U0. 5,4 V0. 5,4 X Y2 U0. 3,2 V0. 3,2 X Y3 U0. 1,0 V0. 1,0
X
X
X
X
X
X
one sequence; X: non valid data
CLK
WEO (WES = 0 status register) line n + 1 WEO (WES = 1 status register) YI0 to YI7 UI0, UI1 VI0, VI1 X Y0 U0. 7,6 V0. 7,6 Y1 U0. 5,4 V0. 5,4 X Y2 U0. 3,2 V0. 3,2 X Y3 U0. 1,0 V0. 1,0
MGK172
X
X
X
X
X
X
one sequence; X: non valid data
Fig.4 Write enable timing.
Va (PIN 22) * Vertical synchronization signal, active HIGH * Minimum HIGH period equals one line period * Vertical synchronization signals converted to system clock domain internally. So the Va pulse can be asynchronous. * See timing diagram Fig.6 and Table 11 for timing specification.
CLK (PIN 19) * Line locked system clock, up to 16 MHz typical * All clock related signals act on the rising edge of the system clock. TST0, TST1 AND TST2 (PINS 26, 25 AND 24) * Test mode inputs * Active HIGH, with internal pull-down resistors.
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
Table 9 Test settings TST1 0 1 X(1) X(1) 0 X(1) X(1) 1 TST0 application mode test mode test mode test mode MODE
SAA4945H
TST2 0 X(1) 1 X(1) Note 1. X = don't care.
SNDA, SNCL AND VRST (PINS 2, 3 AND 4) * Serial interface signals * SNERT bus protocol (Synchronous No parity 8-bit receiver and Transmission bus) * SNDA is a bidirectional signal with 8-bit wide data and address (LSB first) * Serial interface signals converted (internally) to system clock domain. To avoid set-up violations these signals are clocked two times by the system clock before further processing is performed. * Synchronization of serial address (every even byte) and data (every odd byte) by VRST.
handbook, full pagewidth
Tcy(SNCL)
SNCL tsu(i)(D) SNDA (receiver mode) SNDA (transmitter mode) th(D) LSB th(Q)
data valid data valid data valid data valid data valid data valid data valid
MGK173
td(D)
Fig.5 Timing diagram of serial interface.
Table 10 Timing characteristics (see Fig.5) SYMBOL tcy(SNCL) tsu(i)(D) th(D) th(Q) td(D) PARAMETER SNCL cycle time input set-up time input hold time output data hold time output data delay time 1 90 50 0 - MIN. - - - - 700 MAX. s ns ns ns ns UNIT
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
Output signals YO0 TO YO7 (PINS 38 TO 44 AND 1) * 8-bit wide digital luminance output bus * Data format: unsigned, dynamic range between 0 and 255. UO1 AND UO0 (PINS 37 AND 36) * Colour difference signal U * Data format: 2's complement, dynamic range between -128 and +127 * Y : U : V format 4 : 1 : 1; see Table 8. VO1 AND VO0 (PINS 35 AND 34) * Colour difference signal V * Data format: 2's complement, dynamic range between -128 and +127 * Y : U : V format 4 : 1 : 1; see Table 8. WEO (PIN 31) * Write enable output
SAA4945H
* Write enable indicates the time when active samples (Y, U and V) are present * Timing relation (see Fig.6) depending on write enable select signal (WES) in status register; to adapt to different external video memories * The number of output samples is a multiple of 4 * The write enable output sequence is a copy of the write enable input sequence of the previous line (see Fig.6) with a shift of one line * The last line in field is not processed.
handbook, full pagewidth
tVa(min)H
t(Va-WE)LH
Va tsu(Va) VRST t(WE-VRST)LH WEI L(n-1) L(n) L(0) L(1) L(2) t(Va-VRST)LH
WEO
L(n-2)
L(n-1) 1 clk cycle
L(0)
L(1)
internal flag to mask WEO
MGK174
Fig.6 Timing diagram for WEO blanking and Va.
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
Table 11 Va versus VRST SYMBOL tVa(min)H tsu(Va) t(Va-WE)LH t(Va-VRST)LH t(WE-VRST)LH PARAMETER minimum Va HIGH time set-up Va to negative edge of WEI Va LOW to WEI HIGH time Va LOW to VRST HIGH time WEI LOW to VRST HIGH time 64 0 0 0 64
SAA4945H
MIN. s s s s s
UNIT
LIST OF SNERT BUS ADDRESSES USED IN LIMERIC TASTE register Table 12 TASTE register usage USE Purpose Address Read/write Range F3 write 0 to 4; 0 = noise filtering disabled ACTION to set 4 different types of noise reduction
Table 13 TASTE register content MSB 0 0 0 0 ts3 ts2 ts1 LSB ts0 see Table 14 REMARK
Table 14 TASTE setting TS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 noise filtering disabled not applicable noise reduction; TASTE 1 not applicable noise reduction; TASTE 2 not applicable noise reduction; TASTE 3 not applicable noise reduction; TASTE 4 not applicable not applicable not defined not defined not defined not defined not defined FUNCTION
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
Status register Table 15 Status register usage USE Purpose Address Read/write internal settings F4 write ACTION
SAA4945H
Table 16 Status register content MSB Tctrl3 Tctrl2 Tctrl1 X ExThr Wv DEM LSB WES
Table 17 Status register description BIT 0 NAME WES Write Enable Select 0: data coincides with write enable (both input and output) 1: data is delayed over one clock period with respect to the write enable (both input and output) see Fig.4 1 DEM Demo Mode 0: demo mode disabled 1: demo mode on; the noise reduction circuit is switched on for the left half of the screen - the noise reduction is disabled (split screen function) for the right half of the screen 2 Wv Weave 0: enable weave 1: disable weave 3 ExThr External Threshold control bit 0: N_thr calculated by noise estimator 1: value of N_thr from register F9 is used 4 5 X Tctrl1 don't care Test control 1 0: normal operation 1: test mode 6 Tctrl2 Test control 2 0: normal operation 1: test mode 5 Tctrl3 Test control 3 0: normal operation 1: test mode DESCRIPTION
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
Wval register (wanted value) Table 18 Wval register usage USE Purpose Address Read/write Range Table 19 Wval register MSB Wval7 Wval6 Wval5 Wval4 Wval3 Wval2 Wval1 LSB Wval0 Tctrl2 = 0 register for setting up noise estimator F5 write 0 to 255 ACTION
SAA4945H
CONDITIONS
Noise threshold register Table 20 Noise threshold register usage USE Purpose Address Read/write Range F9 write 0 to 255 ACTION register for setting the NTHR value for the noise filter externally
Table 21 Noise threshold register content MSB NTHR[7] NTHR[6] NTHR[5] NTHR[4] NTHR[3] NTHR[2] NTHR[1] LSB NTHR[0]
Noise estimator setting register Table 22 Noise estimator setting register usage USE Purpose Address Read/write FA write ACTION register for general setting of the noise estimator
Table 23 Noise estimator setting register MSB YpScale1 YpScale0 0 0 0 0 0 0 LSB
Table 24 Noise estimator setting description YpScale1 0 0 1 1 1997 Jun 10 YpScale0 0 1 0 1 DESCRIPTION noise estimator pre-filter gain setting = 1 noise estimator pre-filter gain setting = 0.5 noise estimator pre-filter gain setting = 0.25 noise estimator pre-filter bypassed 14
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD1 VDD2 VI Tstg Tamb Ptot PO(pin) supply voltage 1 supply voltage 2 input voltage storage temperature operating ambient temperature total power dissipation output power dissipation per output pin PARAMETER -0.5 -0.5 -0.5 -55 -40 - - MIN. +6.5 +6.5 +6.5 +150 +85 150 100 MAX.
SAA4945H
UNIT V V V C C mW mW
THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 65 UNIT K/W
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
CHARACTERISTICS VDD = 5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supply VDD IDD Tamb Tstg P CLK fCLK VIL VIH CL clock frequency duty cycle LOW-level input voltage HIGH-level input voltage load capacitance 7%; note 1 10 40 - 2 10 - 2.0 VI = 0 to 5 V - 6 7 - 2.4 7 - - - 2.0 - 2.4 - 2.0 16 - - - - - - - - - - - - - - - - - - - - supply voltage (pins 5, 29 and 30) supply current operating ambient temperature storage temperature power dissipation 4.5 - 0 -50 - 5.0 70 - - 350 PARAMETER CONDITIONS MIN. TYP.
SAA4945H
MAX.
UNIT
5.5 - 70 +150 -
V mA C C mW
17.1 60 0.8 - -
MHz % V V pF
YI7 to YI0, UI1, UI2, VI1, VI0, WEI and Va VIL VIH II tsu(i)(D) th(D) LOW-level input voltage HIGH-level input voltage input current set-up time hold time 0.8 - 20 - - V V A ns ns
YO7 to YO0, UO1, UO2, VO1, VO0 and WEO VOL VOH th(Q) td(D) fSNERT VIL VIH VOL VOH VIL VIH Note 1. Maximum number of clocks per line is 1024. LOW-level output voltage HIGH-level output voltage output hold output delay IOL = 1.6 mA IOH = 0.4 mA CL = 15 pF CL = 15 pF 0.4 - - 32 V V ns ns
SNDA and SNCL bus clock frequency LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage 1 0.8 - 0.4 - MHz V V V V
TST0, TST1 and TST2 LOW-level input voltage HIGH-level input voltage 0.8 - V V
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SAA4945H
SOT307-2
c
y X
A 33 34 23 22 ZE
e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA4945H
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC (LIMERIC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4945H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/20/01/pp20
Date of release: 1997 Jun 10
Document order number:
9397 750 01608

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